tpt-silicon
RustOpen-source EDA toolchain: a Rust-based HDL (Silica) compiling to Verilog-2005, plus a full digital design suite — lint, format, synth, sim, place & route, DRC — and a Tauri desktop IDE.
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TPT Silicon + TPT Silica
An open-source EDA (Electronic Design Automation) tool suite, licensed under Apache 2.0.
This repository hosts two related projects, built together as a single Cargo workspace, plus a desktop IDE that ties them together:
- TPT Silica — a hardware description language (HDL) that compiles to Verilog-2005 and to a
native intermediate representation (IR). See
verilog.txtfor the language design. - TPT Silicon — the EDA tool suite (linting, formatting, documentation, synthesis,
simulation, testbenches, physical design) that consumes Verilog and the shared IR. See
spec.txtfor the full design. - TPT Silicon IDE (
tpt-app) — a Tauri-based desktop app that wires the tools above into a single UI.
spec.txt and verilog.txt are the source-of-truth design docs. TODO.md tracks
build progress against them. For deeper documentation than this README, see the
docs/ directory.
Quickstart
git clone https://github.com/tpt-solutions/tpt-silicon.git
cd tpt-silicon
cargo build --workspace
# Scaffold a new Silica project
cargo run -p silica-cli -- new my-project --template counter
cd my-project
cargo run -p silica-cli -- check src/main.silica
cargo run -p silica-cli -- build src/main.silica --backend verilog
Once installed (cargo install --path silica-cli, see Deploy / install),
the binary is just silica, so the same commands become silica new, silica check,
silica build.
Starter templates
silica new <name> --template <template> scaffolds a Silica.toml, src/main.silica,
README.md, .gitignore, and tests/ directory. Four templates are available:
| Template | Description |
|---|---|
counter (default) | Up-counter with synchronous reset and enable — the simplest starting point |
fifo | A 2-entry FIFO buffer exercising registers, wires, and when/otherwise chains |
uart | A UART transmitter state machine, showing enum/match and bit-indexing |
blank | An empty module Main() { } skeleton |
Workspace layout
Silica frontend (built first — produces Verilog + TPT IR consumed by Silicon tools):
| Crate | Role |
|---|---|
silica-parse | Lexer (logos) + recursive-descent parser → AST |
silica-typecheck | Bidirectional type checker |
silica-ir | Typed flattened IR (signals/instances/processes) |
silica-verilog | IR → Verilog-2005 codegen |
silica-tptir | Silica IR → TPT IR (shared interchange format) |
silica-cli | Unified binary: silica parse|check|build|new |
silica-fmt | Pretty-printer for Silica source with configurable style |
silica-lint | Linter for Silica source, pluggable rules + auto-fix |
silica-ls | LSP server for Silica (diagnostics, completion, go-to-def, hover, refactoring) |
Silicon tools (consume Verilog/TPT IR):
| Crate | Role |
|---|---|
tpt-parse | Verilog/SystemVerilog subset parser |
tpt-ir | Shared TPT IR types + bincode serialization |
tpt-lint | Lint rule engine (50 rules, --json output) |
tpt-fmt | Verilog formatter (--check/--write, install-git-hook) |
tpt-doc | Documentation generator (Markdown) |
tpt-synth | RTL → netlist: elaboration, const-fold, bool-simplify, tech-map (sky130) |
tpt-sim | Event-driven 4-state interpreter (0/1/X/Z), VCD output |
tpt-test | Testbench generation + toggle-coverage tracking |
tpt-wave | Waveform viewer (stub — Tauri/WebGPU deferred) |
tpt-pdk | SkyWater 130nm PDK data (cell library, design rules, layer map) |
tpt-layout | Physical layout model (geometry, placement, routing, GDSII I/O) |
tpt-place | Placement & routing engine (floorplan, global/local place, CTS, power grid) |
tpt-drc | Design rule checker (R-tree spatial index, width/spacing/enclosure/antenna/density, LVS) |
tpt-plugin | Plugin system: Pass/PlacePass/LintRule traits, PluginRegistry, built-in optimizers |
tpt-ai | Optional AI integration: Ollama/OpenAI/OpenRouter/Anthropic/MCP clients |
tpt-pkg | Package manager (tpt binary): dependency resolution, tpt add/update/build/test/doc |
Two further workspace members round out the 27 tool/library crates above: tpt-app (the desktop
IDE, see below) and benches (Criterion benchmarks, publish = false, not a distributed tool).
For how these crates depend on each other, see docs/architecture.md or
AGENTS.md.
Desktop IDE
tpt-app/ is a Tauri 2 desktop application (Rust backend in tpt-app/src-tauri/, a Vite/React
frontend in tpt-app/ui/) that hosts the tools above in one UI. See
docs/deployment.md for how to build and bundle it.
Configuration
Tools read an optional tpt-silicon.toml project config (AI, lint, format, and build settings).
See tpt-silicon.toml.example for every field, or
docs/configuration.md for a guided walkthrough. AI integration in
particular has its own guide: docs/ai-integration.md.
Development
cargo build --workspace
cargo test --workspace
cargo fmt --all -- --check # CI checks formatting
cargo clippy --workspace --all-targets -- -D warnings # CI denies warnings
Deploy / install
- Build release binaries:
cargo build --release --workspace(output intarget/release/). - Install a single tool:
cargo install --path silica-cli(or any other tool crate). - Build the desktop app bundle:
cargo tauri build(installer/.dmg/.deb/AppImage per OS).
Full details, prerequisites, and per-OS notes: docs/deployment.md.
Documentation
docs/README.md— full documentation site (getting started, language guide, tool reference, plugin authoring, AI integration, deployment, architecture, configuration).AGENTS.md— repo conventions for AI coding agents.spec.txt/verilog.txt— source-of-truth design specs.
License
Apache 2.0 — see LICENSE.